Package Offerings
From Leadframe to Wafer Level
A Full Spectrum of Packaging Solutions
Our turnkey services cover Package Development, Wafer Probing, Wafer Bumping/WLCSP, Assembly & Packaging, Electrical and Reliability Testing, Failure Analysis, Warehousing and Drop Shipment. Real-time WIP systems and direct OEM drop shipping help customers achieve faster time-to-market.
Unisem also provides standard and custom Leadframe and Laminate packages, ranging from 3 to 484+ pins. Our cost-effective WLCSP solutions enable direct connectivity at the substrate or board level.
Our Exclusive Services
Leaded
Packages
- PDIP
- QSOP
- SOIC
- SSOP
- TSOT
- TSSOP
Leadless
Packages
- SLP
- SLP SIP
- Stacked Die SLP
- MIS Package
Laminate
Packages
MEMs
Packaging
- LGA-FLP Package Outline
- LGA-MCP Package Outline
- LGA-MLP Package Outline
Wafer Level
Packaging
- WLCSP
Core Offering
Tailored Solutions for Complex Demands
Laminate Technology Advantages:
Enhanced electrical insulation, flexible routing, and advanced integration capabilities to power high-performance applications.
Gold Bumping
Reliable interconnects for wire bonding and flip-chip applications.
Our Fine-pitch Ball Grid Array (FBGA) is a chip-scale package designed especially for markets requiring miniaturization, such as hand-held consumer products, cellular phones and laptop computers. The FBGA features a standard BT substrate and fine solder ball pitch, available in 0.5mm and 0.8mm sizes. It also offers the fastest assembly throughput of our fine-pitch packages. This package is also available in an LGA (land grid array) version for an ultra thin profile.
Unisem’s SIP (System-In-Package) technology brings enhanced functionality and integration to our laminate packages making them perfectly suited for wireless and other applications needing system integration in a single package format. Includes multichip and configurations with passives.
Unisem’s Stacked Die BGA can be used to stack 2 or more die in a pyramid style or same die stack resulting in fewer packages and a smaller footprint. This near chip-scale option is assembled using standard FBGA tooling and is also available in LGA format. Wafer thinning, overhang wire bond technology and spacers are used between stacked die. Die to die bonding also can also enhance the thermal and electrical performance.